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Qn #2042
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Qn #1227
Let the memory access time is 10 miliseconds and cache hit ratio 15%. The effective memory access time is
Qn #800
Qn #725
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4 -way set associative. The minimum size of the TLB tag is:
Qn #606
Qn #602
A CPU generates 32 bits virtual
addresses. The page size is 4 KB. The processor has a translation look-aside
buffer (TLB) which can hold a total of 128-page table entries and is 4- way set
associate. The minimum size of the TLB tag is
Qn #600
Qn #424
In computer architecture, which of the following correctly matches the fundamental
unit used in the CPU, cache, and main memory respectively?
Qn #421
In an instruction execution pipeline, the earliest that the instruction TLB and data
TLB
can be accessed are
Qn #85